1. Field of the Invention
This invention generally relates to a circuit for generating a reference voltage, and more particularly to a circuit for generating a reference voltage of an image sensor.
2. Description of Related Art
More and more electronic devices such as mobile phones, PDA, or toys provide built-in cameras. To adapt different applications, especially for the application of mobile devices, an image sensor with low power consumption and high resolution is required. FIG. 1A is a block diagram of a traditional image sensor. Referring to FIG. 1A, the traditional image sensor includes a pixel array 110, a row driver and voltage reference generator 120, a sample and hold column circuit 130, a gain stage 140, and a pipeline A/D converter 150. The row driver and voltage reference generator 120 provides the driver signals 121 for each row, the reference voltage 122, and reference voltage VCL. Each row electrode (not shown) of the pixel array 110 receives the row driver signal 121. The pixel array 110 senses the image and then output the pixel signal 111 to each column according to the row driver signal 121. The sample and hold column circuit 130 receives, samples, and holds the pixel signal 111 of each column, and outputs the cascade pixel signal 131. The gain stage 140 receives and amplifies the cascade pixel signal 131 and generates the pixel signal 141. The A/D converter 150 generally a pipeline A/D converter, which converts the pixel signal 141 to a digital pixel signal 151 according to the reference voltage 122 for the use of the subsequent circuits (such as logic control circuit 160 or other circuits).
In the image sensor readout circuit, the process of generating reference voltage is the major power consumption of the image sensor readout circuit. Taking the sample and hold column circuit 130 of a CMOS image sensor as examples, FIG. 1B is a pixel sample circuit of a CMOS image sensor. Referring to FIG. 1B, to facilitate the illustration, the pixel 112 is used to represent the pixels 112 of the pixel array 110. Further, the pixel sample circuit 130 includes a plurality of sample/hold circuits. In FIG. 1B, only one sample/hold circuit is shown as an example. CMOS image sensor generally will sample a pixel signal voltage and a pixel reset voltage, which requires the reference voltage VCL for sampling. During the sampling period, the sense-control switches clamp and same_sig are close and sense-control switches samp_rst, cb, and col_addr are open. Hence, the voltage difference of the pixel signal voltage and the reference voltage VCL will be stored in the capacitor CS1. During the reset period, the sense-control switches clamp and same_rst are close and sense-control switches samp_sig, cb, and col_addr are open. Hence, the voltage difference of the pixel reset voltage and the reference voltage VCL will be stored in the capacitor CS2. After completing the sampling process, the sense-control switches clamp, samp_sig, and samp_rst become open and the sense-control switch cb becomes close, which is so-called the holding period. During the holding period, the pixel signal 111 of each column will be stored in one of the sample/hold circuits, and each sample/hold circuit based on the clock alternately turns on the sense-control switch col_addr (i.e., close-circuited) to output the cascade pixel signal to the gain stage 140.
In the pixel sample circuit 130, the reference voltage VCL is provided by the voltage generator 120. The voltage generator 120 also provides different reference voltages for the other circuits such as the gain stage 140 and the A/D converter 150. The reference voltage must be a stable and fix voltage. Taking the reference voltage VCL as an example, during the reset period, the right terminal of the capacitor CS2 is coupled to the reference voltage VCL and the left terminal of the capacitor CS2 is coupled to the pixel 112 to receive the reset voltage. When the reset voltage charges the capacitor CS2, the transient response of the capacitor would cause the right terminal of the capacitor CS2 to generate a pulse voltage. This pulse voltage will temporarily change the voltage level of the reference voltage VCL. The voltage generator 120 has to absorb this pulse voltage to make the VCL back to the original level. The pixel sample circuit 130 has to wait until the reference voltage VCL is back to the original level and the capacitor is stable to enter into the holding period. As the pixel array becomes larger, more and more sample/hold circuits are required, which means that the loading of the reference voltage VCL becomes larger and thus the level of the reference voltage VCL is more difficult to maintain. For example, the aforementioned pulse voltage would cause a significant change on the reference voltage level. Hence, it would take longer to go back to the original level. As the pixel array becomes larger, this effect is more significant, which causes a low sampling rate of the image sensor.